this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www.visha y .com v ishay siliconix spice device model tp0101 k document number: 72921 s-52397 ? p-channel 20-v (d-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the typical electrical characteristics of the p-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 5-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact physical interpretation of the device. subcircuit model schematic
2 vishay siliconix spice device model tp0101k www.visha y .com document number: 72921 s-52397 ? c unless otherwise noted) parameter symbol test condition simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = ? 50 a 0.85 v on-state drain current a i d(on) v ds = ? 5 v, v gs = ? 4.5 v 6.4 a v gs = ? 4.5 v, i d = ? 0.58 a 0.43 0.42 drain-source on-state resistance a r ds(on) v gs = ? 2.5 v, i d = ? 0.50 a 0.63 0.64 ? forward transconductance a g fs v ds = ? 5 v, i d = ? 0.58 a 1.3 1.3 s diode forward voltage a v sd i s = ? 0.30 a, v gs = 0 v ? 0.80 ? 0.90 v dynamic b total gate charge q g 1.2 1.4 gate-source charge q gs 0.30 0.30 gate-drain charge q gd v ds = ? 6 v, v gs = ? 4.5 v, i d = ? 0.58 a 0.25 0.25 nc turn-on delay time t d(on) 26 25 rise time t r 25 30 turn-off delay time t d(off) 51 55 fall time t f v dd = ? 6 v, r l = 10 ? i d ? ? 0.58 a, v gen = ? 4.5 v, r g = 6 ? 16 38 ns notes a. pulse test; pulse width 300 s, duty cycle 2%. b. guaranteed by design, not s ubject to production testing.
3 v ishay siliconix spice device model tp0101 k www.visha y .com document number: 72921 s-52397 ? c unless otherwise noted)
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